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CCadence Design Systems

Intern - Characterization and Support (Fall 2026)

San Jose, CAListed 6w ago

  • On-site
  • Internship
  • Fall 2026

About this role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern.  (local candidates will be considered)
Intern will be responsible for validating both system-level and electrical performance of internal silicon test chips. 
The role includes debugging silicon issues in close collaboration with analog and digital design teams, and delivering high-quality characterization reports. 
The intern will work cross-functionally to ensure product functionality, reliability, and successful deployment.
The candidate is expected to be strongly motivated by the prospect of driving system and electrical testing efforts for identifying silicon issues and being involved in debug efforts for the same.
Very good fundamentals in analog and digital electronics, RTL, Signal integrity, control systems.
Strong analytical and problem-solving skills

Requirements
Currently pursuing a Bachelor's or Master’s degree in electrical engineering with 0-2 years of relevant work experience
Excellent written and verbal communication skills
Ability to work collaboratively in a team environment
Prior experience in the hardware semiconductor or electronics industry is a plus
Experience with script-based test automation in Python, C or other scripting tools is a plus.

As this role is expected to be employed in San Jose during the Fall semester, applicants should ideally be attending a local school. Candidate should be able to prove they can work fulltime hours in San Jose during the Fall. Also need to have legal authorization to work in the US.

The annual salary range for California is $40/hr to $69/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

We’re doing work that matters. Help us solve what others can’t.

$40/hrListed pay
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Location
San Jose, CA
Work model
On-site
Role type
Internship
Season
Fall 2026
Family
Validation/Test Engineer
Listed
6w · Aug 29, 2026
C

Cadence Design Systems

Public · 10,001+ employees

  • Semiconductors & Electronics
  • Automotive & Mobility
  • Aerospace & Defense

Cadence Design Systems provides computational software, hardware, and semiconductor IP for electronic-system design and verification. Its portfolio spans digital and custom IC design, verification, chip and interface IP, package and PCB design, and multiphysics analysis. Customers include semiconductor and systems companies in automotive, aerospace, industrial, communications, and other electronics markets.

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